1. Field of the Invention
This invention relates to a method of making a thin film transistor device, more particularly to a method of making a thin film transistor device that involves the use of a gray scale photoresist pattern.
2. Description of the Related Art
Thin film transistors (TFTs) are utilized in various applications, such as liquid crystal displays (LCD). Examples of the thin film transistors include n-type thin film transistors, p-type thin film transistors, complementary metal oxide semiconductor transistors, and poly-silicon transistors. The poly-silicon transistors have recently become popular and are widely used in the LCD industry.
FIG. 1 illustrates an n-type thin film transistor that includes a substrate 11, a semiconductor layer 12 that is formed on the substrate 11, a dielectric layer 13 that is formed on the semiconductor layer 12, a gate electrode 14 that is formed on the dielectric layer 13, source and drain contacts 16 that are respectively formed on source and drain regions 124 of the semiconductor layer 12, source and drain electrodes 15 that are respectively formed on the source and drain contacts 16, and an insulator material 17 that separates the gate electrode 14 apart from the source and drain contacts 16.
The semiconductor layer 12 is made from poly silicon, and includes a central region 121, the n-type source and drain regions 124, and two transition regions 123. Each of the source and drain regions 124 is heavily doped with n+ type dopant. Each of the transition regions 123 is intrinsic or is lightly doped with n− or n type dopant. The dielectric layer 13 covers the central region 121, and is made from a dielectric material that is selected from SiOx, SiNx, insulator material, and combinations thereof.
A conventional method of making the thin film transistor, similar to that disclosed in U.S. Patent Application Publication No. 20040266075, includes the steps of: forming a semiconductor layer on a substrate; forming a dielectric layer on the semiconductor layer; forming a gate-forming layer on the dielectric layer such that the gate-forming layer cooperates with the dielectric layer and the semiconductor layer to define a layered structure; forming a first photoresist pattern on the gate-forming layer such that the first photoresist pattern overlaps a transistor-forming region of the layered structure; removing a blank region of the layered structure, that is not covered by the first photoresist pattern, from the substrate; removing the first photoresist pattern by stripping; forming a second photoresist pattern on the gate-forming layer such that the second photoresist pattern overlaps a gate-defining region, a source transition defining region and a drain transition defining region of the layered structure and exposes a source covering region and a drain covering region of the gate-forming layer that correspond respectively to source and drain regions of the semiconductor layer; removing the source covering region and the drain covering region of the gate-forming layer by etching; doping a dopant into the source and drain regions of the semiconductor layer; removing the second photoresist pattern by stripping; forming a third photoresist pattern on the gate-forming layer such that the third photoresist pattern overlaps the gate-defining region of the layered structure and exposes two transition-covering regions of the gate-forming layer; removing the transition-covering regions of the gate-forming layer by etching so as to expose two cover zones of the dielectric layer that correspond respectively to two transition regions of the semiconductor layer; doping the dopant into the transition regions of the semiconductor layer; removing the third photoresist pattern by stripping; forming source and drain contacts on the source and drain regions of the semiconductor layer, respectively; and forming source and drain electrodes on the source and drain contacts, respectively.
The conventional method is disadvantageous in that it requires too many photolithographic and etching steps for forming the thin film transistor.